Altium

Design Rule Verification Report

Date: 16.08.2023
Time: 9:35:49
Elapsed Time: 00:00:02
Filename: C:\Users\fg77rg\Userdata\_backup\Altium\projects\_RainLight\R124_EVK_V31\PCB\R124_EVK_V31_4layer.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.5mm) (All),(OnLayer('KeepOutLayer')) 0
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Clearance Constraint (Gap=0mm) (All),(WithinRoom('RoomDefinition_TitleBlock')) 0
Clearance Constraint (Gap=0.3mm) ((InPoly)),(All) 0
Clearance Constraint (Gap=0mm) (Disabled)(All),(All) 0
Clearance Constraint (Gap=0.4mm) ((InPoly)),((InPoly)) 0
Clearance Constraint (Gap=0.5mm) ((InPoly)),(IsTrack AND (OnLayer('KeepOutLayer') OR OnLayer('Mechanical1'))) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (not WithinRoom('RoomDefinition_TitleBlock')) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.2mm) (Max=3mm) (Preferred=0.3mm) (All) 0
Routing Via (MinHoleWidth=0.3mm) (MaxHoleWidth=0.6mm) (PreferredHoleWidth=0.3mm) (MinWidth=0.7mm) (MaxWidth=1.3mm) (PreferedWidth=0.8mm) (All) 0
SMD Neck-Down Constraint (Percent=100%) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.5mm) (Conductor Width=0.25mm) (Air Gap=0.25mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.2mm) (not HasFootprint('Lightpipe')) 0
Acute Angle Constraint (Minimum=56.000) (All) 0
Hole Size Constraint (Min=0.3mm) (Max=4mm) (All) 0
Hole To Hole Clearance (Gap=0.25mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.1mm) (IsPad),(All) 0
Silk To Solder Mask (Clearance=0.1mm) (not WithinRoom('RoomDefinition_TitleBlock')),(OnLayer('TopOverlay')) 0
Silk to Silk (Clearance=0mm) (InComponent('R6') or InComponent('R7') or InComponent('R8')),(All) 0
Silk to Silk (Clearance=0.1mm) (not WithinRoom('RoomDefinition_TitleBlock')),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (not WithinRoom('RoomDefinition_TitleBlock')) 0
Vias Under SMD Constraint (Allowed=Not Allowed) (not HasFootprint('QFN50P400X400-24W6L')) 0
Total 0